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Module Details

Course : Computer Architecture And Organisation

Subject : Computer science

No. of Modules : 52

Level : UG

Source : SwayamPrabha;Channel-13

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Sr. No. Title Creator/Author E-Text Video URL Metadata
1 Summarization of the course Prof. Indranil Sengupta & Prof. Kamalika Dutta - - Click Here
2 Multi-core processors Prof. Indranil Sengupta - - Click Here
3 Some case studies Prof. Indranil Sengupta - - Click Here
4 Vector processors Prof. Indranil Sengupta - - Click Here
5 Multicycle operations in mips32 Prof. Indranil Sengupta - - Click Here
6 Pipeline hazards (part 4) Prof. Indranil Sengupta - - Click Here
7 Pipeline hazards (part 3) Prof. Indranil Sengupta - - Click Here
8 Pipelining the mips32 data path Prof. Indranil Sengupta - - Click Here
9 Pipeline hazards (part i) Prof. Indranil Sengupta - - Click Here
10 Pipeline hazards (part 2) Prof. Indranil Sengupta - - Click Here
11 Mips32 data path (contd.) Prof. Indranil Sengupta - - Click Here
12 Exercises on i/o transfer Prof. Indranil Sengupta - - Click Here
13 Universal serial bus (usb) Prof. Indranil Sengupta - - Click Here
14 Bus standard Prof. Indranil Sengupta - - Click Here
15 Some example device interfacing Prof. Indranil Sengupta - - Click Here
16 Direct memory access Prof. Indranil Sengupta - - Click Here
17 Interrupt handling (part ii) Prof. Indranil Sengupta - - Click Here
18 Interrupt handling (part i) Prof. Indranil Sengupta - - Click Here
19 Data transfer techniques Prof. Indranil Sengupta - - Click Here
20 Secondary storage devices Prof. Indranil Sengupta - - Click Here
21 Input-output organization Prof. Indranil Sengupta - - Click Here
22 Arithmatic pipeline Prof. Indranil Sengupta - - Click Here
23 Basic pipelining concepts Prof. Indranil Sengupta - - Click Here
24 Pipeline scheduling Prof. Indranil Sengupta - - Click Here
25 Floating- point arithmatics Prof. Indranil Sengupta - - Click Here
26 Floating- point numbers Prof. Indranil Sengupta - - Click Here
27 Design of dividers Prof. Indranil Sengupta - - Click Here
28 Design of multipliers (part i) Prof. Indranil Sengupta - - Click Here
29 Design of multipliers (part 2) Prof. Indranil Sengupta - - Click Here
30 Design of adders (part ii) Prof. Indranil Sengupta - - Click Here
31 Design of adders (part i) Prof. Indranil Sengupta - - Click Here
32 Improving cache performance Prof. Kamalika Datta - - Click Here
33 Improving cache performence Prof. Kamalika Datta - - Click Here
34 Cache memory (part ii) Prof. Kamalika Datta - - Click Here
35 Cache memory (part i) Prof. Kamalika Datta - - Click Here
36 Memory hierarchy design (part ii) Prof. Kamalika Datta - - Click Here
37 Memory interfacing and addressing Prof. Kamalika Datta - - Click Here
38 Memory hierarchy design (part i) Prof. Kamalika Datta - - Click Here
39 Asynchronous dram Prof. Kamalika Datta - - Click Here
40 Synchronous dram Prof. Kamalika Datta - - Click Here
41 Design of control unit (part 4) Prof. Kamalika Datta - - Click Here
42 Processor memory interaction Prof. Kamalika Datta - - Click Here
43 Mips implementation ( part 2) Prof. Kamalika Datta - - Click Here
44 Mips implementation ( part 1) Prof. Kamalika Datta - - Click Here
45 Static and dynamic ram Prof. Kamalika Datta - - Click Here
46 Design of control unit (part 3) Prof. Kamalika Datta - - Click Here
47 Design of control unit (part 2) Prof. Kamalika Datta - - Click Here
48 Design of control unit (part 1) Prof. Kamalika Datta - - Click Here
49 Amadahl's law (part ii) Prof. Kamalika Datta - - Click Here
50 Sumarizing performance results Prof. Kamalika Datta - - Click Here
51 Amadahl's law (part i) Prof. Kamalika Datta - - Click Here
52 Choice of benchmarks Prof. Kamalika Datta - - Click Here