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Module Details

Course : Hardware Modeling Using Verilog

Subject : Computer science

No. of Modules : 36

Level : UG

Source : SwayamPrabha;Channel-13

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Sr. No. Title Creator/Author E-Text Video URL Metadata
1 Switch level modeling ( part 2) Prof. Indranil Sengupta - - Click Here
2 Switch level modeling ( part 1) Prof. Indranil Sengupta - - Click Here
3 Basic pipelining concepts Prof. Indranil Sengupta - - Click Here
4 Pipeline modeling (part 2) Prof. Indranil Sengupta - - Click Here
5 Pipeline modeling (part 1) Prof. Indranil Sengupta - - Click Here
6 Modeling register banks Prof. Indranil Sengupta - - Click Here
7 Some recommended practices Prof. Indranil Sengupta - - Click Here
8 Modeling memory Prof. Indranil Sengupta - - Click Here
9 Datapath and controller design (part 3) Prof. Indranil Sengupta - - Click Here
10 Synthesizable verilog Prof. Indranil Sengupta - - Click Here
11 Datapath and controller design (part 2) Prof. Indranil Sengupta - - Click Here
12 Datapath and controller design (part 1) Prof. Indranil Sengupta - - Click Here
13 Modeling finite state machines ( contd.) Prof. Indranil Sengupta - - Click Here
14 Modeling finite state machines Prof. Indranil Sengupta - - Click Here
15 Writing verilog test benches Prof. Indranil Sengupta - - Click Here
16 Verilog test bench Prof. Indranil Sengupta - - Click Here
17 Blocking / non- blocking assignments ( part 4) Prof. Indranil Sengupta - - Click Here
18 User - defined primitives Prof. Indranil Sengupta - - Click Here
19 Blocking / non- blocking assignments ( part 3) Prof. Indranil Sengupta - - Click Here
20 Blocking / non- blocking assignments ( part 2) Prof. Indranil Sengupta - - Click Here
21 Blocking / non- blocking assignments ( part 1) Prof. Indranil Sengupta - - Click Here
22 Procedural assignment ( examples) Prof. Indranil Sengupta - - Click Here
23 Procedural assignment ( contd.) Prof. Indranil Sengupta - - Click Here
24 Procedural assignment Prof. Indranil Sengupta - - Click Here
25 Verilog modeling examples ( contd.) Prof. Indranil Sengupta - - Click Here
26 Verilog description styles Prof. Indranil Sengupta - - Click Here
27 Verilog modeling examples Prof. Indranil Sengupta - - Click Here
28 Verilog operators Prof. Indranil Sengupta - - Click Here
29 Verilog language features (part 3) Prof. Indranil Sengupta - - Click Here
30 Verilog language features (part 2) Prof. Indranil Sengupta - - Click Here
31 Verilog language features (part 1) Prof. Indranil Sengupta - - Click Here
32 Vlsi design styles (part 2) Prof. Indranil Sengupta - - Click Here
33 Vlsi design styles (part 1) Prof. Indranil Sengupta - - Click Here
34 Getting started with verilog Prof. Indranil Sengupta - - Click Here
35 Design representation Prof. Indranil Sengupta - - Click Here
36 Introduction Prof. Indranil Sengupta - - Click Here